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1 D2-24044 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. digital audio amplifier power stage D2-24044 the D2-24044 device is a high performance, integrated class-d amplifier power stage. the four power stage outputs are configurable as four separate half-bridge outputs, as two full-bridge outputs, or combinations of half-bridge and full-bridge. individual power stage overload monitoring, on-chip temperature monitoring, and common alert logic outputs provide protection to integrate with the final system?s controller. features ? all digital class-d power stage ? 4 configurable power stage outputs supporting: - 2 channels, bridged - 4 channels, half-bridge - 2 channels, half-bridge, plus 1 channel bridged ? output power (bridged) - 25w (8 , < 1% thd) - 30w (8 , < 10% thd) ? single hv supply - wide 9v-26v range - gate drive supply internally-generated ? individual channel protection monitoring ? temperature and undervoltage monitoring ? efficient 38 ld htssop package digital amplifier power stage reg5v vddhv ocfg0 ocfg1 npdn iref pwm1 pwm2 pwmvdd pwmgnd hvddd outd hgndd hsbsd nerrord hvddc outc hgndc hsbsc nerrorc hvddb outb hgndb hsbsb nerrorb hvdda outa hgnda hsbsa nerrora novrt pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 power supply drivers configuration & control september 3, 2010 fn7678.0
2 fn7678.0 september 3, 2010 ordering information part number (notes 2, 3) part marking application support temp. range (c) package (pb-free) pkg. dwg. # D2-24044-mr D2-24044-mr commercial -10 to +85 38 ld htssop m38.173c D2-24044-mr-t (note 1) D2-24044-mr commercial -10 to +85 38 ld htssop m38.173c notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for the D2-24044 . for more information on msl please see techbrief tb363 . D2-24044
3 fn7678.0 september 3, 2010 table of contents absolute maximum ratings ....................................................................................................... .......... 4 thermal information ............................................................................................................ ............... 4 recommended operating conditions ............................................................................................... .... 4 electrical specifications ...................................................................................................... ................. 4 performance specifications ..................................................................................................... ............ 5 pin configuration.............................................................................................................. ................... 6 pin description ................................................................................................................ .................... 6 typical performance characteristics............................................................................................ ........ 8 full-bridge typical performance curves ......................................................................................... ........ 8 half-bridge typical performance curves ......................................................................................... ....... 9 functional overview ............................................................................................................ .............. 10 output options ................................................................................................................. ................. 10 power supply requirements...................................................................................................... ........ 10 high side gate drive voltage ................................................................................................... .......... 10 supply bypass connection....................................................................................................... .......... 10 reg5v .......................................................................................................................... .................. 10 input and control functions .................................................................................................... .......... 11 pwm inputs..................................................................................................................... ................ 11 npdn input pin ................................................................................................................. ............... 11 nerrora-d output pins.......................................................................................................... .......... 11 novrt output pin ............................................................................................................... ............. 11 iref pin....................................................................................................................... ................... 11 ocfg0, ocfg1 input pins ........................................................................................................ ......... 11 protection..................................................................................................................... ..................... 11 short-circuit and overcurrent sensing .......................................................................................... ...... 11 thermal protection and monitoring .............................................................................................. ....... 12 power supply voltage monitoring ................................................................................................ ....... 12 output mode configurations ..................................................................................................... ......... 14 typical application examples ................................................................................................... ......... 17 2-channel full bridge example.................................................................................................. ......... 17 2.1-channel example............................................................................................................ ............ 18 4-channel half-bridge example.................................................................................................. ........ 19 package outline drawing ........................................................................................................ .......... 20 D2-24044
4 fn7678.0 september 3, 2010 absolute maximum ratings thermal information supply voltage hvdd[a:d], vddhv. . . . . . . . . . . . . . . . . . 0v to +28.0v pwmvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 4.0v input voltage any input . . . . . . . . . . . . . . . . . -0.3v to pwmvdd + 0.3v thermal resistance (typical) ja (c/w) jc (c/w) 38 ld htssop package (notes 4, 5) 29 1.3 maximum storage temperature . . . . . . . . -55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www .intersil.com/pbfree/pb-freer eflow .asp recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . -10c to +85c high voltage supply voltage, hvdd[a:d], vddhv . . . . . . . . . . . . . . . . . . 9.0v to 26.5v digital i/o supply voltage, pwmvdd . . . . . . . . . . . . . . 3.3v minimum load impedance (hvdd[a:d] 24.0v), z l . . . . 4 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. absolute maximum parameters are not tested in production. electrical specifications t a = +25c, pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. parameter test conditions symbol min typ max unit digital input high logic level v ih 2--v digital input low logic level v il - - 0.4 v high level output drive voltage (i out at -pin drive strength current) v oh pwmvdd-0.4 - - v low level output drive voltage (i out at +pin drive strength current) v ol - - 0.4 v input leakage current pins 1, 2, 3 i in - - 10 a pwm input pins (includes 100k internal pull-down resistor current) - - 50 a input capacitance c in -9-pf output capacitance all outputs except out[a:d] c out -9-pf out[a:d] - 190 - internal pull-up resistance to pwmvdd (for nerrora-d, novrt) - 100 - k digital i/o supply pin voltage, current pwmvdd 3 3.3 3.6 v active current - 0.47 - ma power-down current - 0.15 - ma 3.3v (pwmvdd) brown-out detection logic supply undervoltage threshold - 2.6 - v logic supply undervoltage threshold hysteresis - 200 - mv logic supply undervoltage glitch rejection - 50 - ns gate drive internal +5v brown-out detection gate drive supply undervoltage threshold - 4.5 - v D2-24044
5 fn7678.0 september 3, 2010 gate drive supply undervoltage threshold hysteresis - 200 - mv gate drive supply undervoltage threshold glitch rejection -50-ns protection detect high voltage undervoltage protection -79v overcurrent trip threshold -4-a overcurrent de-glitch - 2.5 - ns short-circuit current limit (peak) -8-a overcurrent response time -20-ns thermal shut-down otmax - 140 - c thermal warning temperature otmin - 125 - c thermal shut-down hysteresis -30-c thermal warning hysteresis -20-c electrical specifications t a = +25c, pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. (continued) parameter test conditions symbol min typ max unit performance specifications t a = +25c, pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground . parameter symbol min typ max unit r ds(on) (mosfets @ +25c) r ds(on) - 200 - m r ds(on) mismatch - 1 - % pwm switching rate - 384 - khz minimum pwm pulse width - 3.5 - ns pwm off sensor time - 10 - s pwm input to output delay - 50 ns pwm input to output delay matching - 3 - ns npdn input off delay t pdnoff - 1.4 - npdn input on delay t pdnon - 1.4 - power output <1% thd, bridged, load = 8 , hvdd[a:d] = 24v p out -25-w <10% thd, bridged, load = 8 , hvdd[a:d] = 24v p out -30-w <1% thd, half-bridge, load = 8 , hvdd[a:d] = 24v p out -7-w <10% thd, half-bridge, load = 8 , hvdd[a:d] = 24v p out -9-w thd+n load = 8 , power = 25w, bridged, 1khz thd+n - 0.3 - % load = 8 , power = 1w, bridged, 1khz - 0.05 - % snr snr - 110 - db efficiency (load = 8 )-90-% D2-24044
6 fn7678.0 september 3, 2010 pin configuration D2-24044 38 ld htssop top view 1 2 3 4 5 6 7 8 9 10 11 12 38 37 36 35 34 33 32 28 27 26 25 24 23 13 14 15 16 17 31 30 29 outb hsbsa hsbsb hgndb hvddb reg5v vddhv iref hvddc hgndc outc hsbsc hsbsd outd hgndd hvddd 1 8 1 9 npdn outa pwmgnd hgnda hvdda pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwmgnd2 pwm2 pwm1 novrt pwmvdd ocfg0 ocfg1 n e r r o r a n e r r o r b n e r r o r c n e r r o r d 22 21 20 pin description pin pin name (note 7) type voltage level (v) description 1 npdn i 3.3 power-down and mute input. active low. when this input is low, all 4 outputs become inactive and their output stages float, and their output is muted. internal logic and other references remain active during this power-down state. 2 ocfg1 i 3.3 output configuration control select. ocfg0 and ocfg1 are logic inputs to select the output configuration mode of the output stages. connects to either pwmgnd ground or pwmvdd (+3.3v) through nominal 10k resistor to select output configuration. 3 ocfg0 i 3.3 output configuration control select. ocfg0 and ocfg1 are logic inputs to select the output configuration mode of the output stages. connects to either pwmgnd ground or pwmvdd (+3.3v) through nominal 10k resistor to select output configuration. 4 pwmgnd gnd 0 low-voltage ground. connects to ground of circuitry providing pwm inputs. both pwmgnd and pwmgnd2 are to tie together to the same ground. 5 pwmvdd p 3.3 low-voltage power. this 3.3v supply connects to the same system low-voltage power used for providing pwm inputs. 6 novrt o 3.3 over-temperature warning output. open drain, 16ma drive strength output with pull-up. pulls low when active from over-temperature detection. 7 pwm1 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 8 pwm2 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 9 pwm3 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 10 pwm4 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 11 pwm5 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 12 pwm6 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. D2-24044
7 fn7678.0 september 3, 2010 13 pwm7 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 14 pwm8 i 3.3 pwm input. routes to output channel, dependent on output configuration settings. 15 pwmgnd2 gnd 0 low-voltage ground. connects to ground of circuitry providing pwm inputs. both pwmgnd and pwmgnd2 are to tie together to the same ground. 16 nerrora o 3.3 overcurrent protection output, channel a output stage. open drain, 16ma drive strength output with pull-up. pulls low when active from overcurrent detection of output stage. 17 nerrorb o 3.3 overcurrent protection output, channel b output stage. open drain, 16ma drive strength output with pull-up. pulls low when active from overcurrent detection of output stage. 18 nerrorc o 3.3 overcurrent protection output, channel c output stage. open drain, 16ma drive strength output with pull-up. pulls low when active from overcurrent detection of output stage. 19 nerrord o 3.3 overcurrent protection output, channel d output stage. open drain, 16ma drive strength output with pull-up. pulls low when active from overcurrent detection of output stage. 20 hvddd p hv output stage d high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 21 hgndd gnd hv output stage d high voltage supply ground. a separate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (also see note 8). 22 outd o hv pwm power amplifier output, channel d. 23 hsbsd i hv high side boot strap input, output channel d. capacitor couples to outd amplifier output. 24 hsbsc i hv high side boot strap input, output channel c. capacitor couples to outc amplifier output. 25 outc o hv pwm power amplifier output, channel c. 26 hgndc gnd hv output stage c high voltage supply ground. a separate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (also see note 8). 27 hvddc p hv output stage c high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 28 iref i - overcurrent reference analog input. used in setting the overcurrent error detect externally-set threshold. the pin needs to be connected to a 100k resistor to ground to set the overcurrent threshold according to the specified limits. 29 vddhv p +hv high voltage internal driver supply power. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. the internal +5v supply regulators also operate from this vddhv input. 30 reg5v p 5 5v internal regulator filter connect. a +5v supply is internally generated from the voltage source provided at the vddhv pin. reg5v is used for external connection of a decoupling capacitor. 31 hvddb p hv output stage b high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 32 hgndb gnd hv output stage b high voltage supply ground. a separate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (also see note 8). 33 outb o hv pwm power amplifier output, channel b. 34 hsbsb i hv high side boot strap input, output channel b. capacitor couples to outb amplifier output. 35 hsbsa i hv high side boot strap input, output channel a. capacitor couples to outa amplifier output. 36 outa o hv pwm power amplifier output, channel a. pin description (continued) pin pin name (note 7) type voltage level (v) description D2-24044
8 fn7678.0 september 3, 2010 typical performance characteristics 37 hgnda gnd hv output stage a high voltage supply ground. a separate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (also see note 8). 38 hvdda p hv output stage a high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. notes: 7. unless otherwise specified all pin names are active high. those that are active low have an ?n? prefix, such as nerrora. 8. thermal pad is internally connected to all 4 hgnd ground pins (hgnda, hgndb, hgndc, hgndd). any connection to the thermal pad must be made to the common ground for these 4 ground pins. pin description (continued) pin pin name (note 7) type voltage level (v) description full-bridge typical performance curves figure 1. thd vs power, full-bridge figure 2. thd vs frequency, full-bridge figure 3. frequency response, full-bridge figure 4. noise floor, full-bridge 0.01 10.00 0.02 0.05 0.10 0.20 0.50 1.00 2.00 5.00 thd (%) 0.06 50 0.1 0.2 0.5 1 2 5 10 20 power (w) hvdd = 24.0v, 8 load, 1khz 0.001 1.000 0.002 0.005 0.010 0.020 0.050 0.100 0.200 0.500 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) p = 25w thd (%) p = 14w p = 7w p = 1w hvdd = 24.0v, 8 load, at 1w, 7w, 14w, 25w power out -6 6 -5 -4 -3 -2 -1 -0 1 2 3 4 5 dbr a 30 10k 50 100 200 500 1k 2k 5k frequency (hz) hvdd = 24.0v, 8 load, 3.5w -120 -50 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 dbr a -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs < -115db, un-weighted hvdd = 24.0v, 8 load, at 1khz, reference to 30w D2-24044
9 fn7678.0 september 3, 2010 half-bridge typical performance curves figure 5. thd vs power, half-bridge figure 6. thd vs frequency, half-bridge figure 7. frequency response, half-bridge figure 8. noise floor, half-bridge thd (%) power (w) 0.02 10.00 0.05 0.10 0.20 0.50 1.00 2.00 5.00 0.06 20 0.1 0.2 0.5 1 2 5 10 hvdd = 24.0v, 8 load, 1khz frequency (hz) thd (%) 0.001 1.000 0.002 0.005 0.010 0.020 0.050 0.100 0.200 0.500 20 20 k 50 100 200 500 1k 2k 5k 10k hvdd = 24.0v, 8 load, 2.4w power out -12 12 -10 -8 -6 -4 -2 -0 2 4 6 8 10 20 20k 50 100 200 500 1k 2k 5k 10k dc response without ac response due to loudspeaker dc blocking capacitor dc blocking capacitor dbr a frequency (hz) hvdd = 24.0v, 8 load, 1w -125 -30 -120 -115 -110 -105 -100 -95 -90 -85 -45 -40 -35 -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs dbr a -80 -75 -70 -65 -60 -55 -50 < -110db, un-weighted noise floor @ 1khz, +24v rail, spdif input, 8 load, unity dsp gain D2-24044
10 fn7678.0 september 3, 2010 functional overview the devices include four independent output stages (figure 9) that are each implemented using a high side (to positive vddhv supply) and a low side (to hv supply ground) fet pair. drivers and overcurrent monitoring are included in each of these four output stages. depending on the selected configuration mode, these four stages can be used independently as single half-bridge outputs, or as pairs for full-bridge outputs. digital pwm inputs are connected to the pwm input pins, where their signals are routed through the configuration select logic to the individual output fets and drivers. on-chip temperature and undervoltage monitoring, and individual per-output current monitoring provides protection and status reporting outputs to the system controller. upon application of power, the on-chip voltage sensors monitor presence of the required power voltages. until all voltages are at their design specifications, the outputs remain off and floating. after supply voltages are within limits and stable, the output configuration is set by the logic levels at the ocfg0 and ocfg1 input pins, and the pwm inputs are routed to their appropriate output stage fets. output options the D2-24044 devices provide four configuration options for the outputs. these options are selected by strapping the ocfg0 and ocfg1 pins high or low. these defined configurations include: ? 2 channels of full bridge, 4-quadrant outputs, ? 2 channels of full bridge, 2-quadrant outputs ? 4 channels of half-bridge outputs ? 2 channels half-bridge, plus 1 channel full bridge when a configuration is set that includes a full-bridge output, each input channel?s pwm input signal is routed to the high and low side fets, appropriate for that full bridge operation. note however, that the device can be configured as 4 independent half-bridge outputs (using mode ?11? as described in the configuration assignment table on page 14) and two of those outputs can be used in a full bridge configuration, simply by connecting the appropriate pwm input pins to the input source. this allows flexibility in applications where combinations may be desired other than the four defined by the output configuration modes. power supply requirements the device operates from two supply voltages: ? pwmvdd is a nominal 3.3v supply voltage, and operates the logic and control. ? hvdd (hvdd[a:d], and vddhv) is the ?high voltage? used for operating the output power stages. individual hvdd and its ground (hgnd) pins are included for each of the four power stage outputs, providing channel isolation and low impedance source connections to each of the outputs. a separate vddhv pin is used for the output drivers, and is the source for the on-chip regulated 5v source needed for the drivers. all the hvdd/vddhv pins connect to the same voltage source. pwmvdd is the reference for the pwm inputs and device control logic, and is the same voltage as used by the pwm/system controller. high side gate drive voltage an on-chip bootstrap circuit provides the high-side gate drive voltage used by each output stage. a pin is included for each output channel (hsbs[a:d]) for connection of a capacitor (nominal, 0.22 f/50v) from this pin to that channel?s pwm output. the charge pumping actions uses this capacitor to filter and hold this gate drive voltage, and enables amplifier operation without need of connection to an additional power supply voltage. supply bypass connection power supply bypass capacitors should be connected across each of the power supply connection pins, as: ? four hvdd power pins and their respective hgnd ground pins. these should be a parallel combination of a nominal 100 f and 0.1 f capacitors, located as close as possible to the hvdd/hgnd pin pair. ? a 0.1 f capacitor also is to connect at the vddhv pin. ? the pwmvdd power pin should include a 1 f and 0.1 f capacitor. reg5v the on-chip gate drive power supply operates from the vddhv power input, to produce the 5v supply voltage. the reg5v pin is used for external capacitor connection to filter this regulated voltage. a 1.0 f and 0.1 f capacitor should be connected to this pin, and the connection should be made as close as practical to the pin. no other connection is to be made to this pin. figure 9. output stage hsbsa high-side pwm drive low side pwm drive nerror overcurrent hgnd (gnd) low side fet high side fet (+) hvdd out D2-24044
11 fn7678.0 september 3, 2010 input and control functions pwm inputs eight pwm input pins provide the pwm inputs to the amplifier?s output stages. the pwm input pins are electrically single-ended, referenced to the pwmvdd and pwmgnd supplies. pwm drive to the output stages is provided differentially on-chip, with the pwm input channels mapped to each of the high-side output fets and the low-side output fets that implement the individual power stages. routing and assignment of the pwm input pins to the output fets is defined by the configuration mode. figures 11, 12, 13, and 14 show the mapping of these input pins to the outputs for each of the four configuration modes. all eight input pins however are not always used in each of the configuration modes. for example, in mode ?00?, providing 3-level drive of two channels of full bridge outputs, or in mode ?11? providing four independent half-bridge outputs, one pwm input is dedicated to each of the fets. but in mode ?01? that implements two 2-quadrant full-bridge outputs, only four pwm inputs are used, and the logical high/low states are routed to the fets as needed. npdn input pin the npdn pin is a control input that is used to set the inactive (powered down) state, and also mute the outputs. it operates by turning off drive and internal sources to the pwm outputs, as well as turning off the pwm drive to those outputs. when an overcurrent condition is detected on an output, causing its overcurrent protection to latch and turn off that output, asserting the npdn input resets the device, and clears this overcurrent state. the npdn pin is active low, and inactive when at logic high level. nerrora-d output pins each of the four outputs includes an overload and overcurrent monitor. an overcurrent or overload condition asserts the nerror output for that channel. these outputs are active low, open drain. depending on the output mode configuration and need to monitor more than one output, these nerror pins can be wire-or connected together. novrt output pin the novrt pin is an output that provides warning of a high temperature condition. it is an open drain, active low output. this pin provides only indication of high temperature. iref pin the iref pin is used to control the overcurrent monitoring threshold. a 100k resistor connects from this pin to ground. ocfg0, ocfg1 input pins these two pins are used to define the configuration of the four output stages. they are connected to logic high (pwmvdd) or logic ground (pwmgnd) to set their level. refer to ?output mode configurations? on page 14 for additional reference and definition. protection the D2-24044 device includes monitors for protection of the system as well as the device itself. certain levels of protection are managed on-chip, as shown in figure 10. other protection is integrated at the system level through the system controller, and involves system design decisions based on: ? a short circuit, over-temperature, or undervoltage event will shut down the outputs. ? other operation depends on the pwm/system controller to properly manage full system protection operation. ? power supply sensors shut down the device if supply voltages drop below their design thresholds. ? overload and overcurrent monitors provide dual threshold status of high current conditions, providing both indication, and device shutdown if needed. ? chip temperature monitoring provides dual threshold status of high temperature conditions, providing both indication, and device shutdown if needed. short-circuit and overcurrent sensing each pwm output fet includes a dual-threshold overcurrent sensor. multiple functions occur depending on detection of overcurrent conditions: ? the lower threshold is used to monitor fault conditions after the output stage filter inductor, such as shorts or overloads on the loudspeaker outputs. ? the higher threshold monitors fault conditions of the pwm output pin. ? the nerror output asserts for the channel detecting the fault. ? for the lower level threshold, nerror remains asserted only through the duration of the overcurrent event. ? for the higher level threshold, the output is shut down, and its nerror output is asserted, and these remain latched until the controller acknowledges the fault event by turning off the channel?s pwm drive. (when the output is shutdown, its pwm output pin floats.) D2-24044
12 fn7678.0 september 3, 2010 thermal protection and monitoring an on-chip temperature sensor provides two thresholds of temperature monitoring. if the device reaches the lower threshold, the novrt output is asserted, providing warning indication to an external controller. the low threshold setting provides indication only, and does not have any effect on device operation. ? the lower high-temperature threshold (warning) is set at approximately +125c. if the device reaches the higher threshold, it will drive all four nerrora-d outputs low (active) and shut down the device, in addition to asserting the novrt output. this shutdown in non-latching, and operation will resume automatically when temperature returns to normal. ? the higher high-temperature threshold (over-temp) is set at approximately +140c. power supply voltage monitoring undervoltage monitors are included for the output drive (hvdd) supply voltage, the on-chip generated gate drive (reg5v) supply voltage, and the low-level pwmvdd supply voltage. detection occurs at approximately 2.5v for pwmvdd, approximately 4v for the gate drive supply, and approximately 7v for the hvdd supply. (limits are listed in the electrical specification tables starting on page 4.) if any of the monitored voltages drop below their threshold, the device shuts down its outputs and asserts all four of the nerror outputs. operation resumes normally after the undervoltage condition is cleared. D2-24044
13 fn7678.0 september 3, 2010 npdn novrt n e r r o r b s r over-current (oc) shutdown: oc detect condition is latched, shutting down output. latched shutdown is then cleared after over-current condition has cleared, and pwm data clocking ha s stopped from pwm controller. h v d d u n d e r v o l t a g e d e t e c t o r + 5 v u n d e r v o l t a g e d e t e c t o r p w m v d d u n d e r v o l t a g e d e t e c t o r o v e r - t e m p e r a t u r e d e t e c t o r s o t w a r n i n g ( l o w - l i m i t ) o t s h u t - d o w n ( h i g h - l i m i t ) over-current warning detected (outa) n e r r o r a n e r r o r c n e r r o r d over-current warning detected (outb) over-current warning detected (outc) over-current warning detected (outd) over-current short detect (outa) pwm input to outa from pwm controller pwm present detector p o w e r d o w n o u t a o v e r - c u r r e n t s h u t d o w n o u t a s r over-current short detect (outb) pwm input to outb from pwm controller pwm present detector p o w e r d o w n o u t b o v e r - c u r r e n t s h u t d o w n o u t b s r over-current short detect (outc) pwm input to outc from pwm controller pwm present detector p o w e r d o w n o u t c o v e r - c u r r e n t s h u t d o w n o u t c s r over-current short detect (outd) pwm input to outd from pwm controller pwm present detector p o w e r d o w n o u t d o v e r - c u r r e n t s h u t d o w n o u t d pin pin pin pin pin pin figure 10. protection and monitoring high-level functional operation D2-24044
14 fn7678.0 september 3, 2010 output mode configurations the D2-24044 device supports four amplifier output configuration modes, utilizing the device?s 4 power stage outputs. configuration selection is controlled by the ocfg0 and ocfg1 pins, by connecting them to either a high (+3.3v, pwmvdd = 1) or low (ground = 0) level. settings are chosen based on the output configuration and topology of the design. their connection is to be hard-connected on the design, and they are not intended to be dynamic or subject to change during system operation. for each of the four configurations, the pwm input pin signals route to the individual fets of each of the power stages to implement the channel drive and topology needed for those configurations. figures 11, 12, 13, and 14 show this routing of the pwm inputs to each of the power stages, and how the particular topology is implemented for that configuration. table 1 shows the configuration functions that are defined with the combinations of the ocfg pins, and t hese diagrams show the implementation that is listed in this table. table 1. D2-24044 configuration pwm and output channel assignments config pins config configuration description power stage output nerror channel use ocfg1 ocfg0 outa outb outc outd nerrora nerrorb nerrorc nerrord 0 0 ?00? 2-channel full bridge 3-level pwm drive (ref. figure 11) output channel 1 output channel 2 connect (wire-or) nerrora & nerrorb together. use for output channel 1 protect connect (wire-or) nerrorc & nerrord together. use for output channel 2 protect high-side fet pwm input assignments pwm1 pwm3 pwm5 pwm7 low-side fet pwm input assignments pwm2 pwm4 pwm6 pwm8 0 1 ?01? 2-channel full bridge, 2-quadrant pwm drive (ref. figure 12) output channel 1 output channel 2 connect (wire-or) nerrora & nerrorb together. use for output channel 1 protect connect (wire-or) nerrorc & nerrord together. use for output channel 2 protect high-side fet pwm input assignments pwm1 pwm2 pwm3 pwm4 low-side fet pwm input assignments pwm2 pwm1 pwm4 pwm3 1 0 ?10? 2-channel half-bridge plus 1-channel full bridge (ref. figure 13) output ch. 1 output ch 2 output channel 3 nerrora use for channel 1 protect nerrorb use for channel 2 protect connect (wire-or) nerrorc & nerrord together. use for output channel 3 protect high-side fet pwm input assignments pwm1 pwm3 pwm5 pwm6 low-side fet pwm input assignments pwm2 pwm4 pwm6 pwm5 1 1 ?11? 4-channel half-bridge (ref. figure 14) output ch. 1 output ch 2 output ch. 3 output ch 4 nerrora use for channel 1 protect nerrorb use for channel 2 protect nerrorc use for channel 3 protect nerrord use for channel 4 protect high-side fet pwm input assignments pwm1 pwm3 pwm5 pwm7 low-side fet pwm input assignments pwm2 pwm4 pwm6 pwm8 D2-24044
15 fn7678.0 september 3, 2010 pwm inputs from pwm/system controller channel 1 output channel 2 output pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwm2 pwm1 channel 2 pwm input channel 1 pwm input pwmin1-hi-2 pwmin1-lo-2 pwmin1-lo-1 pwmin1-hi-1 outa (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) outb outc outd pwm1-8 input pins pwm input mapping to output stages configuration 00 2 x 4-quadrant full-bridge outputs pwmin2-hi-1 pwmin2-lo-1 pwmin2-hi-2 pwmin2-lo-2 figure 11. configuration 00 pwm input-to-output power stage mapping pwm inputs from pwm/system controller pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwm2 pwm1 channel 2 pwm input channel 1 pwm input pwmin2-hi pwmin2-lo pwmin1-lo pwmin1-hi outa (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) outb outc outd pwm1-8 input pins pwm input mapping to output stages configuration 01 2 x full bridge , 2-quadrant output channel 2 output channel 1 output figure 12. configuration 01 pwm input-to-output power stage mapping D2-24044
16 fn7678.0 september 3, 2010 pwm inputs from pwm/system controller channel 1 output channel 2 output pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwm2 pwm1 channel 3 pwm input channel 2 pwm input channel 1 pwm input pwmin2-hi pwmin2-lo pwmin1-lo pwmin1-hi pwmin3-hi pwmin3-lo outa (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) outb outc outd pwm1-8 input pins pwm input mapping to output stages configuration 10 2 x half-bridge outputs + 1 x full bridge output channel 2 output figure 13. configuration 10 pwm input-to-output power stage mapping pwm inputs from pwm/system controller channel 1 output channel 2 output channel 3 output channel 4 output pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwm2 pwm1 channel 3 pwm input channel 2 pwm input channel 1 pwm input pwmin2-hi pwmin2-lo pwmin1-lo pwmin1-hi pwmin3-hi pwmin3-lo channel 3 pwm input pwmin4-hi pwmin4-lo outa (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) (hgnd) high side fet low side fet (hvdd) outb outc outd pwm1-8 input pins pwm input mapping to output stages configuration 11 4x half-bridge outputs figure 14. configuration 11 pwm input-to-output power stage mapping D2-24044
17 fn7678.0 september 3, 2010 typical application examples these examples show functional circuit examples of typical applications using the D2-24044 device. (note: these examples are provided to show typical applications only and are not intended to represent complete production-qualified reference designs.) 2-channel full bridge example this example (figure 15) uses configuration mode ?01? to provide two full-bridge loudspeaker output channels. the pwm controller provides input into four pwm input pins. 1 2 3 4 5 6 7 8 9 10 11 12 38 37 36 35 34 33 32 28 27 26 25 24 23 13 14 15 16 17 31 30 29 outb hsbsa hsbsb hgndb hvddb reg5v vddhv iref hvddc hgndc outc hsbsc hsbsd outd hgndd hvddd 1 8 1 9 npdn outa pwmgnd hgnda hvdda pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwmgnd2 pwm2 pwm1 novrt pwmvdd ocfg0 ocfg1 n e r r o r a n e r r o r b n e r r o r c n e r r o r d 22 21 20 +hv +hv +hv +hv gnd gnd gnd gnd 100k 0.1u 0.1u 1u pwmvdd/+3.3 10k npdn 10k pwmin2-hi pwmin2-lo pwmin1-lo pwmin1-hi novrt pwm inputs from pwm/system controller nerror reporting to pwm/system controller configuration 01 2x full bridge outputs for channel 1 output for channel 2 output D2-24044 channel 2 in channel 1 in channel 2 full bridge output filter +hv channel 1 full bridge output filter (no connect) (no connect) (no connect) (no connect) figure 15. 2-channel full bridge example D2-24044
18 fn7678.0 september 3, 2010 2.1-channel example this example (figure 16) uses configuration mode ?10? to provide two independent half-bridge loudspeaker output channels, plus one full-bridge loudspeaker output. the pwm controller provides input into all eight pwm input pins. 1 2 3 4 5 6 7 8 9 10 11 12 38 37 36 35 34 33 32 28 27 26 25 24 23 13 14 15 16 17 31 30 29 outb hsbsa hsbsb hgndb hvddb reg5v vddhv iref hvddc hgndc outc hsbsc hsbsd outd hgndd hvddd 1 8 1 9 npdn outa pwmgnd hgnda hvdda novrt pwmvdd ocfg0 ocfg1 22 21 20 +hv +hv +hv +hv gnd gnd gnd gnd 100k 0.1u 0.1u 1u pwmvdd/+3.3 10k npdn 10k novrt nerror reporting to pwm/system controller configuration 10 2x half bridge outputs, plus 1x full bridge output D2-24044 channel 1 half bridge channel 3 channel 2 channel 1 output filter bias +hv channel 3 full bridge output filter channel 2 half bridge output filter bias +hv +hv pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwmgnd2 pwm2 pwm1 n e r r o r a n e r r o r b n e r r o r c n e r r o r d for channel 1 output for channel 3 output for channel 2 output pwmin2-hi pwmin2-lo pwmin1-lo pwmin1-hi pwmin3-hi pwmin3-lo pwm inputs from pwm/system controller (no connect) (no connect) figure 16. 2-channel half bridge plus 1-channel full bridge example D2-24044
19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www .intersil.com/design/qualit y intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www .intersil.com fn7678.0 september 3, 2010 for additional products, see www .intersil.com/product_tree 4-channel half-bridge example this example (figure 17) uses configuration mode ?11? to provide four independent half-bridge loudspeaker output channels. the pwm controller provides input into all eight pwm input pins. 1 2 3 4 5 6 7 8 9 10 11 12 38 37 36 35 34 33 32 28 27 26 25 24 23 13 14 15 16 17 31 30 29 outb hsbsa hsbsb hgndb hvddb reg5v vddhv iref hvddc hgndc outc hsbsc hsbsd outd hgndd hvddd 1 8 1 9 npdn outa pwmgnd hgnda hvdda novrt pwmvdd ocfg0 ocfg1 22 21 20 +hv +hv +hv +hv gnd gnd gnd gnd 100k 0.1u 0.1u 1u pwmvdd/+3.3 10k npdn 10k novrt pwm inputs from pwm/system controller nerror reporting to pwm/system controller configuration 11 4x half bridge outputs D2-24044 channel 1 half bridge output filter bias +hv channel 2 half bridge output filter bias +hv +hv channel 3 half bridge output filter bias +hv half bridge output filter bias +hv channel 4 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pwmgnd2 pwm2 pwm1 n e r r o r a n e r r o r b n e r r o r c n e r r o r d channel 3 channel 2 channel 1 for channel 1 output for channel 3 output for channel 2 output pwmin2-hi pwmin2-lo pwmin1-lo pwmin1-hi pwmin3-hi pwmin3-lo channel 3 pwmin4-hi pwmin4-lo for channel 4 output figure 17. 4-channel half bridge example D2-24044
20 fn7678.0 september 3, 2010 D2-24044 package outline drawing m38.173c 38 lead heat-sink thin shrink small outline plastic package (htssop) rev 0, 4/10 notes: exposed pad view detail "a" side view typical recommended land pattern top view 9.700.10 1.10 max 0.50 0.09-0.20 0.05/0.15 38 pin 1 id 4 0.900.05 seating plane 1 2 3 see detail "a" 0.10 d a-b c 0.20 c l c m 0.08 a-b 5 0.05 3 b a d c 4.40.10 6.4 d c c 0.17-0.27 4 2x n/2 tips 0.25 h 0.60.10 line parting (1.00) 12 3 3.200.10 4.60.10 (0-8) (1.30) (5.80) (36x 0.50) (38x 0.28) (3.20) (4.60) scale: 30/1 (view rotated 90c.w.) end view 1. die thickness allowable is 0.2790.0127 (0.01100.0005 inches). 2. dimensioning & tolerances per asme. y14.5m-1994. 3. datum plane h located at mold parting line and coincident with lead where lead exits plastic body at bottom of parting line. 4. at reference datum and does not include mold flash or protrusions, and is measured at the bottom parting line. mold flash or protrusions shall not exceed 0.15mm on the package ends and 0.25mm between 5. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.07mm total in excess of 6. this part is compliant with jedec specification mo-153 variation bdt-1 the leads. the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and an adjacent lead should be 0.08mm. (14) typ

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